This book is a comprehensive overview of the discoveries in composition, growth and control of gold-aluminum intermetallic compounds in microelectronic interconnects known as Purple Plague. It focuses on the history of detection, theory, and understanding of the gold/aluminum interface reliability issues.
Purple Plague in Microelectronics presents research on the phenomenon of purple plague from the earliest days to the present. The authors explain intricate scientific aspects to understand cause and effect of this reliability issue in microelectronics in a way that they are understandable by readers from various educational levels, novice to expert, while satiating the needs of the engineering personnel closely associated with work related to the gold-aluminum interfacial integrity. The discovery of void formations leading to porosity in the purple phase and the subsequent failure of the joint are outlined and detailed analyses of various phases, metallurgy and diffusion phenomenon at the gold-aluminum interface are presented. They provide detailed drawings, graphs, charts, models, and tables for easy comprehension of concepts and phenomenon. Various ways of evaluating the quality and reliability of the joint and the relative merits of the methods are explained with the introduction of shear testing and bond resistance testing. The roles of the ingredients in the packaging materials and the gold wire itself are discussed and the related mathematical models are presented.
This book is intended for electronic assembly engineers, design engineers, assembly process development engineers, material scientists, electronic industry supervisors and managers. It is an excellent reference for anyone responsible for defect control and reliability in gold wirebonding.
Syed Sajid Ahmad received the M.Sc. degrees in Physics from the University of the Punjab at Lahore, Pakistan, and Islamabad University (currently, Quaid-i-Azam University), Islamabad, Pakistan. He is currently the Director of Advanced Packaging with CrossFire Technologies. He contributed to quality and reliability enhancement of assembly processes with Intel from 1979 to 1989, especially, wire bond. He contributed to semiconductor packaging development with National Semiconductor in 1990 and managed quality with GigaBit/TriQuint from 1990 to 1991. His major work at Micron Technology from 1991 to 2003 involved materials enhancement resulting in high reliability products and the development and implementation of advanced packaging of semiconductors. At the Center for Nanoscale Science and Engineering, North Dakota State University, from 2003 to 2015, his focus was on enhancing research and manufacturing capabilities at the center in the areas of thin film, thick film, advanced packaging (CSP), and surface mount technology. He has participated in DARPA and NSF Projects and holds 54 U.S. patents.
Richard C. Blish II received the B.S. degree in Physics and the Ph.D. degree in Materials Science from California Institute of Technology, Pasadena, in 1963 and 1967, respectively., He spent two years with Bell Laboratories, Murray Hill, NJ, on the PicturePhone project; 11 years with Signetics, San Jose, CA, doing analytical chemistry, 15 years with Intel, Santa Clara, CA, in Package Reliability, 11 years with Advanced Micro Devices (AMD), Sunnyvale, CA, as an AMD Fellow in reliability modeling, and is currently a Spansion Fellow. He has been granted 42 patents and has published more than 40 papers on a wide variety of reliability topics.